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| HT32F12365/ht32f12366/ht32f22366 datasheet 32-bit arm ? cortex ? -m3 microcontroller, up to 256 kb flash and 128 kb sram with 1 msps adc, usart, uart, spi, i 2 c, i 2 s, mctm, gptm, bftm, pdma, sci, crc, rtc, wdt, aes, ebi, csif and usb2.0 fs revision: v1.00 date: ?ove??e? 0?? ?01? ?ove??e? 0?? ?01?
rev. 1.00 ? of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 table of contents table of contents 1 general description ................................................................................................ 6 2 features ................................................................................................................... 7 co?e ....................................................................................................................................... ? on-chip me?o?y .................................................................................................................... ? flash me?o?y cont?olle? C fmc ............................................................................................ ? reset cont?ol unit C rstcu ................................................................................................. 8 clock cont?ol unit C ckcu .................................................................................................... 8 powe? manage?ent C pwrcu ............................................................................................. 8 exte?nal inte??upt/event cont?olle? C exti ............................................................................ 9 analog to digital conve?te? C adc ........................................................................................ 9 analog co?pa?ato? C cmp .................................................................................................... 9 i/o po?ts C gpio .................................................................................................................. 10 moto? cont? ol ti?e? C mctm .............................................................................................. 10 pwm gene?ation and captu? e ti?e?s C gptm .................................................................. 11 basic function ti ?e? C bftm ............................................................................................. 11 watchdog ti ?e? C wdt ....................................................................................................... 11 real ti ? e clock C rtc ....................................................................................................... 1? inte?-integ?ated ci?cuit C i ? c ................................................................................................ 1? se?ial pe?iphe?al inte?face C spi ......................................................................................... 1? unive?sal synch? onous asynch?onous receive? t ?ans?itte? C usart ............................. 13 unive? sal asynch?onous receive? t ?ans?itte? C uart ...................................................... 13 s?a?t ca?d inte?face C sci ................................................................................................. 14 inte?-ic sound C i ? s ............................................................................................................. 14 cyclic redundancy check C crc ....................................................................................... 14 pe?iphe?al di?ect me?o? y access C pdma ......................................................................... 15 exte?nal bus inte?face C ebi ................................................................................................ 15 unive?sal se?ial bus device cont?olle? C usb .................................................................... 16 advanced enc?yption standa? d C aes ................................................................................ 16 secu?e digital input output C sdio ..................................................................................... 16 cmos senso? inte?face C csif (ht3?f??366 only) .......................................................... 1? de?ug suppo?t ..................................................................................................................... 1? package and ope? ation te?pe?atu?e .................................................................................. 1? 3 overview ................................................................................................................ 18 device info??ation ............................................................................................................... 18 block diag?a? ..................................................................................................................... 19 rev. 1.00 3 of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 table of contents table of contents me?o?y map ........................................................................................................................ ?0 clock st?uctu?e .................................................................................................................... ?3 4 pin assignment ..................................................................................................... 24 5 electrical characteristics ..................................................................................... 34 a?solute maxi?u? ratings ................................................................................................. 34 reco??ended dc ope?ating conditions ........................................................................... 34 on-chip ldo voltage regulato ? cha?acte?istics ................................................................. 34 powe? consu?ption ............................................................................................................ 35 reset and supply monito? cha?acte?istics ........................................................................... 36 exte?nal clock cha?acte?istics ............................................................................................. 3? inte?nal clock cha?acte?istics .............................................................................................. 38 pll cha ?acte?istics .............................................................................................................. 38 usb pll cha ?acte?istics ..................................................................................................... 39 me?o?y cha?acte?istics ....................................................................................................... 39 i/o po?t cha?acte?istics ........................................................................................................ 39 adc cha?acte?istics ............................................................................................................ 41 co?pa?ato? cha?acte?istics ................................................................................................. 4? gptm/mctm cha?acte?istics .............................................................................................. 43 i ? c cha?acte?istics ............................................................................................................... 43 spi cha?acte?istics .............................................................................................................. 44 i ? s cha?acte?istics ............................................................................................................... 46 sdio cha?acte?istics ........................................................................................................... 48 csif cha?acte?istics ............................................................................................................ 49 usb cha?acte?istics ............................................................................................................. 49 6 package information ............................................................................................ 51 saw type 46-pin (6.5 ??4.5??) qf? outline di?ensions ............................................. 5? 48-pin lqfp ( ??????) outline di?ensions ................................................................... 53 64-pin lqfp ( ??????) outline di?ensions ................................................................... 54 100-pin lqfp (14 ??14??) outline di?ensions ............................................................. 55 rev. 1.00 4 of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 list of tables list of tables ta ?le 1. featu?es and pe?iphe?al list ..................................................................................................... 18 ta ?le ?. registe? map ............................................................................................................................. ?1 ta ? le 3. pin assign?ent fo? 46-pin qf?? 48/64/100-pin lqfp package ............................................... ?8 ta ?le 4. pin desc?iption .......................................................................................................................... 31 ta ? le 5. a?solute maxi?u? ratings ....................................................................................................... 34 ta ?le 6. reco??ended dc ope?ating conditions ................................................................................. 34 ta ?le ?. ldo cha?acte?istics .................................................................................................................. 34 ta ?le 8. powe? consu?ption cha?acte?istics ......................................................................................... 35 ta ?le 9. v dd powe? reset cha?acte?istics .............................................................................................. 36 ta ? le 10. lvd/bod cha?acte?istics ........................................................................................................ 36 ta ? le 11. high speed exte?nal clock (hse) cha?acte?istics .................................................................. 3? ta ?le 1?. low speed exte?nal clock (lse) cha?acte?istics ................................................................... 3? ta ?le 13. high speed inte?nal clock (hsi) cha?acte?istics .................................................................... 38 ta ?le 14. low speed inte?nal clock (lsi) cha?acte?istics ...................................................................... 38 ta ? le 15. pll cha?acte?istics ................................................................................................................. 38 ta ? le 16. usb pll cha?acte?istics ......................................................................................................... 39 ta ?le 1?. flash me?o?y cha?acte?istics ................................................................................................. 39 ta ?le 18. i/o po?t cha?acte?istics ........................................................................................................... 39 ta ? le 19. adc cha?acte?istics ................................................................................................................ 41 ta ?le ?0. co?pa?ato? cha?acte?istics .................................................................................................... 4? ta ?le ?1. gptm/mctm cha?acte?istics ................................................................................................. 43 ta ?le ??. i ? c cha?acte?istics ................................................................................................................... 43 ta ?le ?3. spi cha?acte?istics .................................................................................................................. 44 ta ?le ?4. i ? s cha?acte?istics ................................................................................................................... 46 ta ?le ?5. sdio cha?acte?istics ............................................................................................................... 48 ta ?le ?6. csif elect?ical cha?acte?istics ................................................................................................ 49 ta ?le ??. usb dc elect?ical cha?acte?istics .......................................................................................... 49 ta ?le ? 8. usb ac elect?ical cha?acte?istics ........................................................................................... 50 rev. 1.00 5 of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 list of tables list of figures list of figures figu?e 1. block diag?a? ......................................................................................................................... 19 figu?e ?. me?o?y map ............................................................................................................................ ?0 figu?e 3. clock st?uctu?e ........................................................................................................................ ?3 figu?e 4. 46-pin qf? pin assign?ent ................................................................................................... ?4 figu? e 5. 48-pin lqfp pin assign?ent ................................................................................................... ?5 figu? e 6. 64-pin lqfp assign?ent ......................................................................................................... ?6 figu?e ? . 100-pin lqfp assign?ent ....................................................................................................... ?? figu? e 8. adc sa?pling ?etwo?k model ................................................................................................ 4? figu?e 9. i ? c ti ? ing diag?a?s ................................................................................................................ 44 figu? e 10. spi ti?ing diag?a?s C spi maste? mode ............................................................................. 45 figu? e 11. spi ti?ing diag?a?s C spi slave mode with cpha=1 ......................................................... 46 figu?e 1? . ti?ing of i ? s maste? mode .................................................................................................... 4? figu? e 13. ti?ing of i ? s slave mode ...................................................................................................... 4? figu?e 14. sdio default mode ............................................................................................................... 48 figu?e 15. sdio high-speed mode ........................................................................................................ 49 figu? e 16. usb signal rise ti? e and fall ti?e and c? oss-point voltage (v crs ) defnition .................. 50 rev. 1.00 6 of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 general description 1 general description these devices are high performance, low power consumption 32-bit microcontrollers based around an arm ? cortex ? -m3 processor core. the cortex ? -m3 is a next-generation processor core which is tightly coupled with nested vectored interrupt controller (nvic), systick timer, and includes advanced debug support. the devices operate at a frequency of up to 96 mhz with a flash accelerator to obtain maximum effciency. they provide up to 256 kb of embedded flash memory for code/data storage and 128 kb of embedded sram memory for system operation and application program usage. a variety of peripherals, such as adc, i 2 c, usart, uart, spi, i 2 s, pdma, gptm, mctm, sci, ebi, crc- 16/32, aes-128/256, usb2.0 fs, sdio, csif and swj-dp (serial wire and jtag debug port), etc., are also implemented in the devices series. several power saving modes provide the fexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications. the above features ensure that the devices are suitable for use in a wide range of applications, especially in areas such as white goods application control, power monitors, alarm systems, consumer products, handheld equipment, data logging applications, motor control, fingerprint recognition and so on. rev. 1.00 ? of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 general description features 2 features core } 32-bit arm ? cortex ? -m3 processor core } up to 96 mhz operating frequency } single-cycle multiplication and hardware division } integrated nested vectored interrupt controller (nvic) } 24-bit systick timer the cortex ? -m3 processor is a general-purpose 32-bit processor core especially suitable for products requiring high performance and low power consumption microcontrollers. it offers many special features such as a thumb-2 instruction set, hardware divider, low latency interrupt respond time, atomic bit-banding access and multiple buses for simultaneous accesses. the cortex ? -m3 processor is based on the armv7 architecture and supports both thumb and thumb-2 instruction sets. on-chip memory } } } supports multiple boot modes the arm ? cortex ? -m3 processor is structured using harvard architecture which uses a separate evvufuhrihflvuflrvdgrdgvruhgdd7hlvuflrfrghdggddduher located in the same memory address space but in different address ranges. the maximum address range of the cortex ? lvghrlvelevdgguhvvlgggllrddsuhghhg memory map is provided by the cortex ? -m3 processor to reduce the software complexity of repeated implementation for different device vendors. however, some regions are used by the arm ? cortex ? -m3 system peripherals. refer to the arm ? cortex ? -m3 technical reference manual irupruhlirupdlr)luhvrvhphprupdsrih+7)vhulhvri ghlfhvlfglrgh6shulshuddgrhusuhghhguhlrv flash memory controller C fmc } } 32-bit word programming with in system programming interface (isp) and in application programming (iap) } flash protection capability to prevent illegal access the flash memory controller, fmc, provides all the necessary functions and pre-fetch buffer for the embedded on-chip flash memory. since the access speed of the flash memory is slower than the cpu, a wide access interface with a pre-fetch buffer and cache are provided for the flash memory in order to reduce the cpu waiting time which will cause cpu instruction execution ghdv)dvhprurugsurudpsdhhudvhiflrvduhdvrsurlghg rev. 1.00 8 of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 features reset control unit C rstcu } supply supervisor: 3rhu2hvh3rhurhvh323 urrhhfru2 3urudppdehr9rdhhhfru9 the reset control unit, rstcu, has three kinds of reset, a power on reset, a system reset and an 3luhvh7hsrhuruhvhnrdvdfrguhvhuhvhvhivvhpgulsrhus a system reset resets the processor core and peripheral ip components with the exception of the 6:-3frurhu7huhvhvfdehulhuhgedhhudvldlhudhhvdghuhvh generators. clock control unit C ckcu } } } operating temperature } internal 32 khz rc oscillator } integrated system clock pll } independent clock divider and gating bits for peripheral clock sources 7hrfnrurl.surlghvdudhrirvfldrudgfrfniflrv7hvhlfgh a high speed internal rc oscillator (hsi), a high speed external crystal oscillator (hse), a low speed internal rc oscillator (lsi), a low speed external crystal oscillator (lse), a phase rfnrrs3d+6(frfnprlrufrfnsuhvfdhuvfrfnplshhuv3frfngllghu dgdlfluflu7hfrfnvrih+3dgruh ? -m3 are derived from the system frfn.6<6lffdfrphiurph6,6(+6,+6(ru37h:dfgr7lphudg real time clock (rtc) use either the lsi or lse as their clock source. the maximum operating iuhthfrihvvhpfruhfrfn.+fdehsr+ power management C pwrcu } single v dd srhuvss9r9 } } v 7 battery power supply for rtc and backup registers } three power domains: v dd 9dgdfns } power consumption can be regarded as one of the most important issues for many embedded vvhpdsslfdlrvffruglh3rhururl3:lhvhghlfhvsurlghvpd shvrisrhuvdlprghvvfdv6hhshhs6hhshhs6hhsdg3rhurprgh these operating modes reduce the power consumption and allow the application to achieve the best udghriiehhhhfrlflghpdgvri3rshudllphvshhgdgsrhufrvpslr rev. 1.00 9 of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 features features external interrupt/event controller C exti } } } source trigger type includes high level, low level, negative edge, positive edge, or both edge } } } independently. analog to digital converter C adc } } } } conversion range: v ref+ ~ v ref- elplfdhlvlhudhglhghlfh7huhduhplshhgfdhvlf lfghhhudddrvldfdhvdglhudfdhvfdehphdvuhg,ihls rdhlvuhtluhgruhpdllldvshflfuhvrglgrddr:dfgriflr will monitor and detect these signals. an interrupt will then be generated to inform the device that the input voltage is not within the preset threshold levels. there are three conversion modes to convert an analog signal to digital data. the adc can be operated in one shot, continuous and discontinuous conversion modes. analog comparator C cmp } two rail-to-rail comparators } } } programmable hysteresis } programming speed and consumption } } } comparator has interrupt generation capability with wakeup mcu from sleep or deep sleep prghvurh(7,frurhu the two general purpose comparators (cmp) are implemented within the device. they can be fruhghlhudvvdgdrhfrpsdudruvrufrpelhglhgliihuhnlgvrishulshud,3 each comparator is capable of asserting interrupts to the nvic or wakeup the mcu sleep or deep 6hhsprghvur(7,dnhshhpddhphl rev. 1.00 10 of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 features i/o ports C gpio } } } range of applications. 7h3,2sruvduhslvduhglrhudhudlhiflrvrredlpdlppiflrd ihlellrhsdfndhslv7h3,2slvfdehvhgdvdhudlhiflrdslve frulhfruuhvsrgluhlvhuvuhdughvvrihlsrursslv 7hhhudlhuusvrh3,2slvrihghlfhdhuhdhgfrurdgfriludlr uhlvhuvlh(hud,huusrurl(7, motor control timer C mctm } } } input capture function } } } } } encoder interface controller with two inputs using quadrature decoder } supports 3-phase motor control and hall sensor interface } the pulse widths of input signals or generating output waveforms such as compare match outputs, 3:rsvrufrpshphdu3:rsvlghdglphlvhulr7h7vssruvd encoder interface controller to an incremental encoder with two inputs. the mctm is capable of offering full functional support for motor control, hall sensor interfacing and brake input. rev. 1.00 11 of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 features features pwm generation and capture timers C gptm } } } input capture function } } } } encoder interface controller with two inputs using quadrature decoder 7hhhud3usrvh7lphufrvlvvrirhelsgrfrhuirueldsuhrpsduh hlvhuvvrhelrhuhrdghlvhudgvhhudfrurvdvuhlvhuv they can be used for a variety of purposes including general time measurement, input signal pulse lgphdvuhphrsdhiruphhudlrvfdvvlhsvhhhudlrru3:rs generation. the gptm supports an encoder interface using a decoder with two inputs. basic function timer C bftm } } } counting when a compare match event occurs. watchdog timer C wdt } } interrupt or reset event for the system } programmable watchdog timer window function } register write protection function 7h:dfgr7lphulvddugduhlplflufldfdehvhgrghhfvvhpidluhvghr vriduhpdiflrv,lfghvdelfrgrfrhudsuhvfdhud:7frhudh uhlvhud:7ghddhuhlvhulhuusuhdhgfluflv:7rshudlrfrurfluflu dgd:7surhflrphfdlvp7h:dfgr7lphufdehrshudhgldlhuusprghru duhvhprgh7h:dfgr7lphulhhudhdlhuusruduhvhhhfrhufrv grdguhdfhvdhurdh,ihvriduhgrhvruhrdghfrhudhehiruhd:dfgr 7lphughurrffuvdlhuusruduhvhlehhhudhghhfrhughurv, addition, an interrupt or reset is also generated if the software reloads the counter when the counter dhlvuhdhudruhtdrh:7ghddh7lvphdvhfrhupvehuhrdghg lldlplhglpllgrvldvshflilfphrg7h:dfgr7lphufrhufdeh stopped while the processor is in the debug mode. there is a register write protect function which fdehhdehgrsuhhliurpfdlh:dfgr7lphufrudlrhshfhg rev. 1.00 1? of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 features real time clock C rtc } 32-bit up-counter with a programmable prescaler } alarm function } control register, a prescaler, a compare register and a status register. most of the rtc circuits are rfdhglhdfnsrpdlhfhsiruh3lhuidfh7h3lhuidfhlvrfdhglh v srhugrpdl7huhiruhllvhfhvvdurehlvrdhgiurph,62vlddfrphviurp the power control unit when the v power domain is powered off, that is when the device enters the power-down mode. the rtc counter is used as a wakeup timer to generate a system resume signal from the power-down mode. inter-integrated circuit C i 2 c } } provide an arbitration function and clock synchronization } } supports slave multi-addressing mode with maskable address the i 2 c module is an internal circuit allowing communication with an external i 2 c interface which is an industry standard two line serial interface used for connection to external hardware. these two serial lines are known as a serial data line, sda, and a serial clock line, scl. the i 2 c module surlghvuhhgddudvihuudhvn+lh6dgdugprghn+lh)dvprgh dg+lh)dvprghsvprgh7h6shulrghhudlruhlvhulvvhgrvhs different kinds of duty cycle implementations for the scl pulse. the sda line which is connected directly to the i 2 c bus is a bi-directional data line between the master and slave devices and is used for data transmission and reception. the i 2 c module also has an arbitration detect function and clock synchronization to prevent situations where more than one master attempts to transmit data to the i 2 c bus at the same time. serial peripheral interface C spi } supports both master and slave mode } frequency of up to (f 3. +irupdvhuprghdgi 3. +iruvdhprgh } } multi-master and multi-slave operation the serial peripheral interface, spi, provides an spi protocol data transmit and receive function in both master and slave mode. the spi interface uses 4 pins, which are the serial data input and rslhv,62dg26,hfrfnlh6.dghvdhvhhflh6(2h63,ghlfh dfvdvdpdvhughlfhlffrurvhgddrvlh6(dg6.vldvrlglfdhh start of data communication and the data sampling rate. to receive a data byte, the streamed data elvduhdfhgrdvshflffrfnhghdgvruhglhgdduhlvhurulh),)2dd transmission is carried out in a similar way but in a reverse sequence. the mode fault detection provides a capability for multi-master applications. rev. 1.00 13 of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 features features universal synchronous asynchronous receiver transmitter C usart } supports both asynchronous and clocked synchronous serial communication modes } asynchronous operating baud rate up to (f 3. +dgvfurrvrshudludhsr (f 3. + } full duplex communication } fully programmable serial communication characteristics including: :rughruelfdudfhu parity: even, odd, or no-parity bit generation and detection 6rselruvrselhhudlr lrughu6uvru6uvudvihu } error detection: parity, overrun and frame error } } irda sir encoder and decoder } } the universal synchronous asynchronous receiver transceiver, usart, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. the usart is used to translate data between parallel and serial interfaces, and is commonly used for rs232 standard communication. the usart peripheral function supports four types of interrupt including line 6dv,huus7udvplhu),)2(ps,huushfhlhu7uhvrghhhdfl,huus dg7lph2,huus7h67prghlfghvdehudvplhu),)27),)2dg dehuhfhlhu),)2),)27hvriduhfdghhfd67huuruvdveuhdglh line status register, lsr. the status includes the type and the condition of transfer operations as hdvvhhudhuurufrgllrvuhvliurp3dul2huu)udpldguhdnhhv universal asynchronous receiver transmitter C uart } asynchronous serial communication operating baud-rate up to (f 3. + } full duplex communication } fully programmable serial communication characteristics including: :rughruelfdudfhu parity: even, odd or no-parity bit generation and detection 6rselruvrselhhudlr lrughu6uvru6uvudvihu } error detection: parity, overrun and frame error the universal asynchronous receiver transceiver, uart, provides a flexible full duplex data exchange using asynchronous transfer. the uart is used to translate data between parallel and serial interfaces, and is commonly used for rs232 standard communication. the uart peripheral function supports line status interrupt. the software can detect a uart error status by reading the line status register, lsr. the status includes the type and the condition of transfer operations dvhdvvhhudhuurufrgllrvuhvliurp3dul2huu)udpldguhdnhhv rev. 1.00 14 of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 features smart card interface C sci } } character mode } single transmit buffer and single receive buffer } } 9-bit guard time counter } 24-bit general purpose waiting time counter } parity generation and checking } automatic character retry on parity error detection in transmission and reception modes 7h6pdudug,huidfhlvfrpsdlehlh,62vdgdug7lvlhuidfhlfghv dug,vhulrhprdghhflr6,gddudvihufrurrlfdggddeiihuvlhud timer counters and corresponding control logic circuits to perform all the necessary smart card operations. the smart card interface acts as a smart card reader to facilitate communication with the external smart card. the overall functions of the smart card interface are controlled by a series of registers including control and status registers together with several corresponding interrupts which are generated to get the attention of the microcontroller for sci transfer status. inter-ic sound C i 2 s } master or slave mode } mono and stereo } } } } the i 2 s is a synchronous communication interface that can be used as a master or slave to exchange data with other audio peripherals, such as adcs or dacs. the i 2 s supports a variety of gddirupdv,dggllrrhvhuhr,6mvlhghimvlhgdglmvlhgprghvhuh duhprr3prghvlelvdpshvlh:hh, 2 s operates in the master mode, then when using the fractional divider, it can provide an accurate sampling frequency output and vssruhudhfruriflrdghlrihrsiuhthfrdrlgvvhpsurehpv caused by the cumulative frequency error between different devices. cyclic redundancy check C crc } 2 } } 32 26 23 22 7 4 2 } rev. 1.00 15 of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 features features } } programmable crc initial seed value } data } supports pdma to complete a crc computation of a block of memory the crc calculation unit is an error detection technique test algorithm which is used to verify data transmission or storage data correctness. a crc calculation takes a data stream or a block of data dvlsdghhudhvdelruelrsuhpdlghu2uglduldgddvuhdplvvihge a crc code and used as a checksum when being sent or stored. therefore, the received or restored data stream is calculated by the same generator polynomial as described above. if the new crc code result does not match the one calculated earlier, that means data stream contains a data error. peripheral direct memory access C pdma } } } } 4-level programmable channel priority } auto reload mode } supports trigger source: 63,(,677, 2 c, i 2 63776,(66,2dgvriduh request the peripheral direct memory access controller, pdma, moves data between the peripherals dghvvhpphprurh+ev(df3fdhdvdvrufhdgguhvvghvldlr address, block length and transfer count. the pdma can exclude the cpu intervention and avoid interrupt service routine execution. it improves system performance as the software does not need to join each data movement operation. external bus interface C ebi } programmable interface for various memory types } } memory bank regions and independent chip select control for each memory bank } programmable timings to support a wide range of devices } includes page read mode } different } } srdgguhvvlhv srelgddevlg the external bus interface is able to access external parallel interface devices such as sram, flash and lcd modules. the interface is memory mapped into the internal address map of the rev. 1.00 16 of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 features cpu. the data and address lines are multiplexed in order to reduce the number of pins required to connect to the external devices. the read/write timing of the bus can be adjusted to meet the timing specifcation of the external devices. note the interface only supports asynchronous 8-bit or 16-bit bus interface. universal serial bus device controller C usb complies with usb 2.0 full-speed (12 mbps) specifcation on-chip usb full-speed transceiver 1 control endpoint (ep0) for control transfer 3 single-buffered endpoints for bulk and interrupt transfer 4 double-buffered endpoints for bulk, interrupt and isochronous transfer 1024 bytes ep-sram used as the endpoint data buffers the usb device controller is compliant with the usb 2.0 full-speed specifcation. there is one control endpoint known as endpoint 0 and seven configurable endpoints. a 1024 bytes sram is used as the endpoint buffer. each endpoint buffer size is programmable using corresponding registers, which provides maximum fexibility for various applications. the integrated usb full- speed transceiver helps to minimize the overall system complexity and cost. the usb functional block also contains the resume and suspend feature to meet the requirements of low-power consumption. advanced encryption standard C aes supports aes encrypt / decrypt function supports aes ecb/cbc/ctr mode supports key size 128, 192 and 256 bits supports 4 words initial vector for cbc and ctr mode 8 32 bits ( each in and out fifo capacity ) for 2 aes data blocks supports dma interface supports word data swap function the aes core supports encryption and decryption function. aes only supports 128 bits input data to do encryption or decryption. hardware does not pad any bits of input data. software need to do pad action at frst. secure digital input output C sdio supports two different data bus modes: 1-bit (default) and 4-bit supports two different speed modes: normal speed (default) and high speed sd clock frequency of up to 48 mhz spi mode and mmc stream mode not supported the sdio includes a command register, argument register, response registers, data buffer, timeout counter and error detection logic. the sdio supports single block and multi-block data transfers and is compatible with the pdma, minimizing processor intervention for large data transfers. rev. 1.00 1? of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 features features cmos sensor interface C csif (ht32f22366 only) } } } up to (f +. +lsslhfrfniuhthf } } hardware window capture function } fractional hardware sub-sample function } or cpu 7h266hvru,huidfhrhulvhnrdvh6,)surlghvdlhuidfhirulpdh fdsuhiurp26vhvruv7hghlfhfdehfrhfhgrh26vhvrugluhfvllv 266hvru,huidfh7h6,)vssruver9hulfd6 rev. 1.00 19 of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 overview overview block diagram ? ? ote: the ahb pe?iphe?al function? csif ? is only availa?le in the ht3?f??366. figure 1. block diagram rev. 1.00 ?0 of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 overview memory map rese?ved 0x400c_a000 rese?ved rese?ved rese?ved rese?ved rese?ved rese?ved cmp rese?ved 0x4004_a000 rese?ved rese?ved rese?ved 0x400?_?000 rese?ved 0x400?_5000 rese?ved usb gpioa~e ebi ?56 kb on-chip flash 0x0000_0000 rese?ved 0x0004_0000 boot loade? 0x1f00_0000 rese?ved 0x1f00_?000 option ?yte alias 0x1ff0_0000 ?56 kb 8 kb 1 kb rese?ved 0x1ff0_0400 code sram pe?iphe?al up to 1?8 kb on-chip sram 0x?000_0000 rese?ved 0x?00?_0000 sram ?it ?and alias 0x??00_0000 rese?ved 0x???0_0000 up to 1?8 kb ? mb apb pe?iphe?als 0x4000_0000 ahb pe?iphe?als 0x4008_0000 rese?ved 0x4010_0000 apb/ahb ?it ?and alias 0x4?00_0000 rese?ved 0x4400_0000 p?ivate pe?iphe?al ?us 0xe000_0000 rese?ved 0xe010_0000 0xffff_ffff 51? kb 51? kb 3? mb usart0 0x4000_0000 uart0 0x4000_1000 spi0 0x4000_4000 rese?ved 0x4000_5000 adc 0x4001_0000 0x4001_1000 rese?ved afio 0x400?_?000 rese?ved 0x400?_3000 exti 0x400?_4000 i?s 0x400?_6000 mctm0 0x400?_c000 0x400?_d000 mctm1 usart1 0x4004_0000 uart1 0x4004_1000 sci0 0x4004_3000 rese?ved 0x4004_5000 spi1 0x4004_4000 i?c0 0x4004_8000 rese?ved 0x4005_9000 i?c1 0x4004_9000 rese?ved 0x4006_9000 wdt 0x4006_8000 rese?ved 0x4006_b000 rtc/pwrcu 0x4006_a000 gptm0 0x4006_e000 rese?ved 0x400?_0000 gptm1 0x4006_f000 bftm0 0x400?_6000 rese?ved 0x400?_8000 bftm1 0x400?_?000 apb0 apb1 fmc 0x4008_0000 rese?ved 0x4008_?000 ckcu/rstcu 0x4008_8000 crc-16/3? 0x4008_a000 pdma 0x4009_0000 0x4009_8000 0x400a_0000 rese?ved 0x400b_0000 0x400f_ffff ahb ebi selection bank rese?ved 0x6000_0000 0x?000_0000 64 mb x 4 aes csif sdio 0x400a_8000 0x400c_8000 0x400c_c000 rese?ved sci1 0x4003_a000 0x400?_e000 0x4000_?000 0x4003_c000 0x4004_?000 0x4005_8000 0x4008_c000 0x4009_?000 0x4009_a000 0x400a_?000 0x400a_c000 0x400b_a000 figure 2. memory map rev. 1.00 ?1 of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 overview overview table 2. register map start address end address peripheral bus 0x4000_0000 0x4000_0fff usart0 apb0 0x4000_1000 0x4000_1fff uart0 0x4000_?000 0x4000_3fff rese?ved 0x4000_4000 0x4000_4fff spi0 0x4000_5000 0x4001_9fff rese?ved 0x4001_0000 0x4001_0fff adc 0x4001_1000 0x400?_1fff rese?ved 0x400?_?000 0x400?_?fff afio 0x400?_3000 0x400?_3fff rese?ved 0x400?_4000 0x400?_4fff exti 0x400?_5000 0x400?_bfff rese?ved 0x400?_6000 0x400?_6fff i?s 0x400?_?000 0x400?_bfff rese?ved 0x400?_c000 0x400?_cfff mctm0 0x400?_d000 0x400?_dfff mctm1 0x400?_e000 0x4003_afff rese?ved 0x4003_a000 0x4003_afff sci1 0x4003_c000 0x4003_ffff rese?ved 0x4004_0000 0x4004_0fff usart1 apb1 0x4004_1000 0x4004_1fff uart1 0x4004_?000 0x4004_?fff rese?ved 0x4004_3000 0x4004_3fff sci0 0x4004_4000 0x4004_4fff spi1 0x4004_5000 0x4004_?fff rese?ved 0x4004_8000 0x4004_8fff i?c0 0x4004_9000 0x4004_9fff i?c1 0x4004_a000 0x4005_?fff rese?ved 0x4005_8000 0x4005_8fff cmp 0x4005_9000 0x4006_?fff rese?ved 0x4006_8000 0x4006_8fff wdt 0x4006_9000 0x4006_9fff rese?ved 0x4006_a000 0x4006_afff rtc/pwrcu 0x4006_b000 0x4006_dfff rese?ved 0x4006_e000 0x4006_efff gptm0 0x4006_f000 0x4006_ffff gptm1 0x400?_0000 0x400?_5fff rese?ved 0x400?_6000 0x400?_6fff bftm0 0x400?_?000 0x400?_?fff bftm1 0x400?_8000 0x400?_ffff rese?ved rev. 1.00 ?? of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 overview start address end address peripheral bus 0x4008_0000 0x4008_1fff fmc ahb 0x4008_?000 0x4008_?fff rese?ved 0x4008_8000 0x4008_9fff ckcu/rstcu 0x4008_a000 0x4008_bfff crc-16/3? 0x4008_c000 0x4008_ffff rese?ved 0x4009_0000 0x4009_1fff pdma cont ?ol registe?s 0x4009_?000 0x400c_bfff rese?ved 0x4009_8000 0x4009_9fff ebi cont?ol registe?s 0x4009_a000 0x4009_ffff rese?ved 0x400a_0000 0x400a_1fff sdio 0x400a_?000 0x400a_?fff rese?ved 0x400a_8000 0x400a_9fff usb cont?ol registe?s 0x400a_a000 0x400a_bfff usb sram 0x400a_c000 0x400a_ffff rese?ved 0x400b_0000 0x400b_1fff gpioa 0x400b_?000 0x400b_3fff gpiob 0x400b_4000 0x400b_5fff gpioc 0x400b_6000 0x400b_?fff gpiod 0x400b_8000 0x400b_9fff gpioe 0x400b_a000 0x400c_?fff rese?ved 0x400c_8000 0x400c_9fff aes 0x400c_a000 0x400c_bfff rese?ved 0x400c_c000 0x400c_dfff csif 0x400c_e000 0x400f_ffff rese?ved rev. 1.00 ?3 of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 overview overview clock structure 4~16 mhz hse xtal 8 mhz hsi rc 3? khz lsi rc legend: hse = high speed exte?nal clock hsi = high speed inte?nal clock lse = low speed exte?nal clock lsi = low speed inte?nal clock 3?.?68 khz lse osc wdtsrc pllsrc ahb p?escale? 1???4?8?16?3? fclk ( f?ee ?unning clock) hclkd ( to pdma) stclk (to systick) ck_adc ip ck_wdt wdte? ck_ref ck_hsi/16 ck_hse/16 ck_sys/16 ckout ckoutsrc[?:0] hsee? hsie? lsee? (?ote1) lsie? (?ote1) f ck_sys,max = 96 mhz ck_lsi ck_lse ck_ahb/16 ck_hsi ck_hse pclk ( opax? afio? adc? spix? usartx? uartx? i?cx? i?s? gptmx? mctmx? bftmx? exti? rtc? sci? wdt) pll clock monito? plle? ck_lse ck_pll dmae? adce? ck_lsi hclks ( to sram) hclkf ( to flash) cm3e? fmce? cm3e? srame? 1 0 rtcsrc (?ote1) ck_rtc rtce? (?ote1) 1 0 1 0 ?ote 1: those cont?ol ?its a?e located at rtc cont?ol registe? (rtc_ctrl) ck_ahb 000 001 010 011 100 101 110 ck_sys sw[?:0] 8 ck_usb f ck_usb = 48mhz usbe? hclkc ( to co?tex ? -m3) cm3e? (cont?ol ?y hw) p?escale? 1 ~ 3? ck_ref ck_ebi ( to ebi) ebie? divide? ? hclkbm ( to bus mat?ix) cm3e? bme? hclkapb0 ( to apb0 b?idge) cm3e? apb0e? hclkapb1 ( to apb1 b?idge) cm3e? apb1e? ck_crc ( to crc) crce? pe?iphe?als clock p?escale? 1???4?8 p?escale? 1? ? adc p?escale? 1???4?6?8... 00 01 10 11 pclk pclk/? pclk/4 pclk/8 spie? scie? ck_gpio ( to gpio po?t) gpioee? gpioae? ckrefe? hsi auto t?i??ing cont?olle? ck_lse usb f?a?e pulse ck_sdio ( to sdio) sdioe? ck_aes ( to aes) aese? usbpllsrc usb pll usbplle? 1 0 usbsrc 0 1 00x 011 010 111 110 usbpre ckrefpre ck_usbpll p?escale? 1 ~ 3? csifmpre divide? ? ck_mck csifme? csif_mck f csif_mck f ck_csif /3 mhz ck_csif ( to csif) csife? figure 3. clock structure rev. 1.00 ?4 of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 pin assignment 4 pin assignment pb9 vdda pb11 pb10 pb8 pb? pb6 pb5 pb4 pb? pb3 45 44 43 4? 41 40 39 38 3? 36 35 1 ? 3 4 5 6 ? 8 10 11 1? 13 14 15 16 1? 18 19 ?0 3? 31 30 ?9 ?8 ?? ?6 ?5 ?4 pa1 pa? pa3 pa4 pa5 pa6 pa? vdd_? pb1 pb0 pa10 xtali? af0 (default) af0 (default) af0 (default) vdd_1 vss_1 nrst vbat x3?ki? x3?kout rtcout pd5 xtalout pd4 p33 bak 33v bak p33 bak 33v bak 33v bak 33v p15 33v 33v 33v 33v 33v 33v 33v ap HT32F12365/12366/22366 46 qfn-a 34 9 ?1 cldo af0 (default) p33 33v 33v p33 33v 33v pc13 pc14 pc15 pb14 pb15 af1 af1 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v pa0 46 33v pa8_ boot0 ?? 33v pa9_ boot1 ?3 33v 33 p33 ap p15 33v 33v 3.3 v digital powe? pad 3.3 v analog powe? pad 1.5 v powe? pad 3.3 v digital & analog io pad 3.3 v digital i/o pad bak backup do?ain pad 33v 33v vss ap vssa p33 vss_? 33v 33v 33v 33v usbdm/ pb1? usbdp/ pb13 usb usb jtrst jtdi jtck/ swclk jtdo jtms/ swdio pa11 pa1? pa13 pa14 pa15 usb usb phy pad figure 4. 46-pin qfn pin assignment rev. 1.00 ?5 of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 pin assignment pin assignment vssa pb9 vdda pb11 pb10 pb8 pb? pb6 pb5 pb4 pb? pb3 48 4? 46 45 44 43 4? 41 40 39 38 1 ? 3 4 5 6 ? 8 9 10 11 13 14 15 16 1? 18 19 ?0 ?1 ?? ?3 35 34 33 3? 31 30 ?9 ?8 ?? ?6 ?5 pa0 pa1 pa? pa3 pa4 pa5 pa6 pa? vdd_3 usbdm/ pb1? usbdp/ pb13 vss_? vdd_? pb1 pb0 jtrst jtdi pa10 pa9_ boot1 pa8_ boot0 xtali? af0 (default) af0 (default) af0 (default) vdd_1 vss_1 nrst vbat x3?ki? x3?kout rtcout pd5 xtalout pd4 p33 bak 33v bak p33 bak 33v bak 33v bak 33v 33v 33v 33v p15 usb usb 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v ap ap 3? 1? ?4 36 cldo af0 (default) 33v vss_3 p33 p33 p33 33v 33v 33v p33 p33 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v jtck/ swclk jtdo jtms/ swdio pa11 pa1? pa13 pc13 pc14 pc15 pb14 pb15 af1 af1 33v 33v p33 ap p15 33v 3.3 v digital powe? pad 3.3 v analog powe? pad 1.5 v powe? pad 3.3 v digital & analog i/o pad usb usb phy pad bak backup do?ain pad 33v 3.3 v digital i/o pad pa14 pa15 33v 33v HT32F12365/12366/22366 48 lqfn-a figure 5. 48-pin lqfp pin assignment rev. 1.00 ?6 of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 pin assignment 64 63 6? 61 60 59 58 5? 56 55 54 1 ? 3 4 5 6 ? 8 9 10 15 1? 18 19 ?0 ?1 ?? ?3 ?4 ?5 ?6 ?? 4? 46 45 44 43 4? 41 40 39 38 3? pa0 pa1 pa? pa3 pa4 pa5 pa6 pa? vdd_3 usbdm/ pb1? usbdp/ pb13 vss_? vdd_? pb1 pb0 pa10 xtali? af0 (default) af1 af0 (default) af0 (default) af1 vdd_1 vss_1 nrst vbat x3?ki? x3?kout pc13 pc14 rtcout pc15 pb14 pb15 pd5 xtalout pd4 vssa pb9 vdda pb11 pb10 pb8 pb? pb6 pc? p33 bak 33v bak p33 bak 33v bak 33v bak 33v 33v 33v 33v p15 usb usb 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v ap ap 53 16 ?8 48 cldo pc8 af0 (default) 33v vss_3 p33 p33 p33 33v 33v 33v 33v 33v 33v p33 p33 11 1? 13 pc9 pc11 pc1? 14 pc10 ?9 30 31 pc0 pd0 pc1 pc? 3? 5? 51 50 pb5 pb4 pb? 49 pb3 36 35 34 33 pa9_ boot1 pa8_ boot0 pc3 33v 33v 33v 33v 33v 33v 33v pc5 pc4 pc6 p33 p33 vdd_4 vss_4 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v p33 ap p15 33v 3.3 v digital powe? pad 3.3 v analog powe? pad 1.5 v powe? pad 3.3 v digital & analog i/o pad usb usb phy pad bak backup do?ain pad jtrst jtdi jtck/ swclk jtdo jtms/ swdio pa11 pa1? pa13 pa14 pa15 33v 3.3 v digital i/o pad 33v 33v HT32F12365/12366/22366 64 lqfn-a figure 6. 64-pin lqfp assignment rev. 1.00 ?? of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 pin assignment pin assignment 100 99 98 9? 96 95 94 93 9? 91 81 1 ? 3 4 5 6 ? 8 14 15 ?? ?6 ?? ?8 ?9 30 31 3? 33 34 35 36 66 65 64 63 6? 61 60 59 58 5? 56 pa0 pa1 pa? pa3 pa4 pa5 pa6 pa? vdd_3 usbdm usbdp vss_? vdd_? pb1 pb0 pa10 xtali? af0 (default) af1 af0 (default) af0 (default) af1 vdd_1 vss_1 nrst vbat x3?ki? x3?kout pc13 pc14 rtcout pc15 pb14 pb15 vss_5 xtalout vdd_5 vssa pb9 vdda pb11 pb10 pb8 pb? pb6 pc? p33 p33 bak 33v bak p33 bak 33v bak 33v bak 33v 33v 33v 33v p15 usb usb 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v ap ap 80 ?3 3? 6? cldo pc8 af0 (default) 33v vss_3 p33 p33 33v p33 p33 33v 33v 33v 33v p33 p33 9 10 11 pe8 pe10 pe11 1? pe9 38 39 40 pd1 pd0 pd? pd3 41 33v ?9 ?8 ?? pb5 pb4 pb? ?6 pb3 55 54 53 5? pa9_ boot1 pa8_ boot0 pd8 33v 33v 33v 33v 33v 33v 33v pc5 pc4 pc6 33v 33v 33v 33v 33v 33v 33v 33v 33v pe1? 13 33v 16 1? 18 pc9 pc11 pc1? 19 pc10 33v 33v 33v 33v pd6 ?0 33v ?1 pb1? pb13 ?4 33v 33v ?c ?5 4? 43 pd4 pd5 pc0 44 45 46 pc1 pc? pc3 4? 33v 33v 33v 48 49 50 33v 83 pe1 8? pe? 33v 33v 85 pe3 84 33v 8? 86 pe4 33v 89 pe5 88 pe6 33v 33v 90 pe? 33v 51 pd? 68 pd9 69 pd10 ?0 pd11 ?? ?1 pd13 pd1? 33v 33v ?4 ?3 pd15 pd14 33v 33v ?5 pe0 33v pe13 pe14 pe15 33v 33v 33v p33 p33 vdd_4 vss_4 33v 33v ap ap vref- vref+ 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v 33v p33 ap p15 33v 3.3 v digital powe? pad 3.3 v analog powe? pad 1.5 v powe? pad 3.3 v digital & analog i/o pad usb usb phy pad bak backup do?ain pad 33v 3.3 v digital i/o pad jtrst jtdi jtck/ swclk jtdo jtms/ swdio pa11 pa1? pa13 pa14 pa15 HT32F12365/12366/22366 100 lqfn-a figure 7. 100-pin lqfp assignment rev. 1.00 ?8 of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 pin assignment table 3. pin assignment for 46-pin qfn, 48/64/100-pin lqfp package package alternate function number af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 100 lqfp 64 lqfp 48 lqfp 46 qfn system default gpio adc cmp mctm /gptm spi usart /uart i 2 c sci ebi i 2 s sdio csif n/a n/a system other 1 1 1 46 pa0 adc_ i?0 gt1_ ch0 spi1_ sck usr0_ rts i?c1_ scl sci0_ clk i?s_ ws csif_ d0 ? ? ? 1 pa1 adc_ i?1 gt1_ ch1 spi1_ mosi usr0_ cts i?c1_ sda sci0_ dio i?s_ bclk sd_ dat1 csif_ d1 3 3 3 ? pa ? adc_ i?? gt1_ ch? spi1_ miso usr0_ tx i?s_ sdo sd_ dat ? csif_ d? 4 4 4 3 pa3 adc_ i?3 gt1_ ch3 spi1_ sel usr0_ rx i?s_ sdi sd_ dat3 csif_ d3 5 5 5 4 pa4 adc_ i?4 gt0_ ch0 spi0_ sck usr1_ tx i?c0_ scl sci1_ clk sd_ cmd csif_ d4 6 6 6 5 pa5 adc_ i?5 gt0_ ch1 spi0_ mosi usr1_ rx i?c0_ sda sci1_ dio sd_ clk csif_ d5 ? ? ? 6 pa6 adc_ i?6 gt0_ ch? spi0_ miso usr1_ rts sci1_ det sd_ dat0 csif_ d6 8 8 8 ? pa ? adc_ i?? gt0_ ch3 spi0_ sel usr1_ cts i?s_ mclk csif_ d? 9 pe8 adc_ i?8 spi1_ sel usr0_ rts csif_ hsy?c 10 pe9 adc_ i?9 spi1_ sck usr0_ cts csif_ vsy?c 11 pe10 adc_ i?10 spi1_ mosi usr0_ tx csif_ pck 1? pe11 adc_ i? 11 spi1_ miso usr0_ rx csif_ mck 13 pe1? adc_ i?1? 14 9 9 vdd_3 15 10 10 ep* vss_3 16 11 pc9 adc_ i?13 gt0_ ch0 spi1_ sel ur0_tx i?c1_ scl sd_ dat0 csif_ hsy?c 1? 1? pc10 adc_ i?14 gt0_ ch1 spi1_ sck ur0_rx i?c1_ sda sd_ dat1 csif_ vsy?c 18 13 pc11 adc_ i?15 gt0_ ch? spi1_ mosi sd_ dat ? csif_ pck 19 14 pc1? gt0_ ch3 spi1_ miso sd_ dat3 csif_ mck ?0 pd6 gt0_ eti ebi_ ?rdy ?1 15 11 8 pb1? mt1_ ch? usr0_ tx i?c0_ scl csif_ d? ?? 15 11 8 usbdm ?3 16 1? 9 usbdp ?4 16 1? 9 pb13 mt1_ ch?? usr0_ rx i?c0_ sda csif_ d6 ?5 ?c ?6 1? 13 10 cldo ?? 18 14 11 vdd_1 ?8 19 15 1? vss_1 ?9 ?0 16 13 nrst 30 ?1 1? 14 vbat 31 ?? 18 15 x3?ki? pc13 3? ?3 19 16 x3?kout pc14 33 ?4 ?0 1? rtcout pc15 wakeup 34 ?5 pd0 mt1_ eti i?c0_ sda ebi_a18 i?s_ sdi sd_ cmd 35 pe13 i?c0_ scl ebi_a19 i?s_ mclk 36 pe14 gt1_ eti ebi_a?0 i?s_ ws 3? pe15 gt1_ ch0 ur0_tx ebi_a?1 rev. 1.00 ?9 of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 pin assignment pin assignment package alternate function number af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 100 lqfp 64 lqfp 48 lqfp 46 qfn system default gpio adc cmp mctm /gptm spi usart /uart i 2 c sci ebi i 2 s sdio csif n/a n/a system other 38 ?6 ?1 18 xtali ? pb14 39 ?? ?? 19 xtalout pb15 40 vdd_5 41 vss_5 4? pd1 gt1_ ch1 ur0_rx ebi_a?? i?s_ bclk 43 pd? gt1_ ch? ebi_a?3 i?s_ sdo 44 pd3 gt1_ ch3 ebi_a?4 i?s_ sdi 45 ?8 ?3 ?0 pd4 mt1_ ch0 spi0_ sel i?c1_ scl sci1_ clk ebi_a16 i?s_ mclk sd_ clk csif_ d5 46 ?9 ?4 ?1 pd5 mt1_ ch0? spi0_ sck i?c1_ sda sci1_ dio ebi_a1? sd_ cmd csif_ d4 4? 30 pc0 gt1_ ch0 spi1_ sel ebi_ ad13 i?s_ ws sd_ dat1 48 31 pc1 gt1_ ch1 spi1_ sck ebi_ ad14 i?s_ bclk sd_ dat ? 49 3? pc? gt1_ ch? spi1_ mosi ur1_tx i?c0_ scl ebi_ ad15 i?s_ sdo sd_ dat3 50 33 pc3 gt1_ ch3 spi1_ miso ur1_rx i?c0_ sda sci1_ det ebi_cs3 i?s_ sdi sd_ dat0 51 pd? i?c1_ scl ebi_a? 5? pd8 i?c1_ sda ebi_a0 53 34 ?5 ?? pa8_ boot0 usr0_ tx sci1_ clk i?s_ mclk ckout 54 35 ?6 ?3 pa9_ boot1 spi0_ mosi sci1_ dio ebi_a1 i?s_ ws 55 36 ?? ?4 pa10 mt1_ ch1 usr0_ rx sci0_ det sd_ dat0 csif_ d? 56 3? ?8 ?5 jtdo pa11 mt1_ ch1? spi0_ miso sci1_ det ebi_a0 i?s_ mclk traceswo 5? 38 ?9 ?6 jtck/ swclk pa1 ? 58 39 30 ?? jtms/ swdio pa13 59 40 31 ?8 jtdi pa14 mt0_ ch0 spi1_ sel usr1_ tx sci0_ clk ebi_ad0 csif_ hsy?c 60 41 3? ?9 jtrst pa15 mt0_ ch0? spi1_ sck usr1_ rx sci0_ dio ebi_ad1 csif_ vsy?c 61 4? vdd_? 6? 43 vss_? 63 44 33 30 pb0 mt0_ ch1 spi1_ mosi usr0_ tx i?c0_ scl ebi_ad? csif_ pck 64 45 34 31 pb1 mt0_ ch1? spi1_ miso usr0_ rx i?c0_ sda ebi_ad3 csif_ mck 65 46 pc4 mt1_ ch? usr1_ rts sci0_ clk ebi_ ad10 sd_ clk 66 4? pc5 mt1_ ch?? usr1_ cts sci0_ dio ebi_ ad11 sd_ cmd 6? 48 pc6 mt1_ ch3 sci0_ det ebi_ ad1? sd_ dat0 68 pd9 spi0_ sel ebi_a3 69 pd10 spi0_ sck ebi_a4 ?0 pd11 spi0_ mosi ebi_a5 ?1 pd1? spi0_ miso ebi_a6 ?? pd13 spi1_ sel ebi_a? rev. 1.00 30 of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 pin assignment package alternate function number af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 100 lqfp 64 lqfp 48 lqfp 46 qfn system default gpio adc cmp mctm /gptm spi usart /uart i 2 c sci ebi i 2 s sdio csif n/a n/a system other ?3 pd14 spi1_ sck ebi_a8 ?4 pd15 spi1_ mosi ebi_a9 ?5 pe0 spi1_ miso ebi_a10 35 3? vdd_? 36 33 vss_? ?6 49 3? 34 pb? mt0_ ch? spi0_ sel ur0_tx ebi_ad4 csif_ d0 cki? ?? 50 38 35 pb3 mt0_ ch?? spi0_ sck ur0_rx ebi_ad5 csif_ d1 ?8 51 39 36 pb4 mt0_ brk spi0_ mosi ur1_tx ebi_ad6 csif_ d? ?9 5? 40 3? pb5 mt1_ brk spi0_ miso ur1_rx ebi_ad? csif_ d3 80 53 pc? mt0_ ch3 i?c0_ scl ebi_ad8 sd_ cmd 81 54 pc8 mt0_ eti i?c0_ sda ebi_ad9 sd_ clk 8? pe1 mt1_ ch0 usr1_ tx sci0_ clk ebi_a11 83 pe? mt1_ ch0? sci0_ dio ebi_a1? 84 pe3 mt1_ ch1 ebi_a13 85 55 vdd_4 86 56 vss_4 8? pe4 mt1_ ch1? i?c1_ scl ebi_a14 sd_ dat0 88 pe5 mt1_ ch? usr1_ rx i?c1_ sda ebi_a15 sd_ dat1 89 pe6 mt1_ ch?? usr1_ rts ebi_bl0 i?s_ bclk sd_ dat ? 90 pe? mt1_ brk usr1_ cts ebi_bl1 i?s_ mclk sd_ dat3 91 5? 41 38 pb6 c?0 mt1_ ch0 spi1_ sel ur1_tx ebi_oe i?s_ mclk csif_ d4 9? 58 4? 39 pb? cp0 mt1_ ch0? spi1_ sck ebi_cs0 csif_ d5 93 59 43 40 pb8 cout0 spi1_ mosi ur1_rx ebi_we csif_ d6 94 60 44 41 pb9 c?1 mt1_ ch? spi1_ miso ur0_tx sci1_ clk ebi_ale i?s_ bclk sd_ dat1 csif_ d? 95 61 45 4? pb10 cp1 mt1_ ch?? i?c1_ scl sci1_ det ebi_cs1 i?s_ sdo sd_ dat ? 96 6? 46 43 pb11 cout1 mt1_ ch3 ur0_rx i?c1_ sda sci1_ dio ebi_cs? i?s_ sdi sd_ dat3 9? 63 4? 44 vdda 98 63 4? 44 vref+ 99 64 48 45 vref- 100 64 48 45 vssa ? ote: the ep is ?eant the exposed pad of the qf? package. rev. 1.00 31 of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 pin assignment pin assignment table 4. pin description pin number pin name type (1) i/o structure (2) output driving description 100 lqfp 64 lqfp 48 lqfp 46 qfn default function (af0) 1 1 1 46 pa0 ai/o 33v 4/8/1?/16 ?a pa0 ? ? ? 1 pa1 ai/o 33v 4/8/1?/16 ?a pa1 3 3 3 ? pa ? ai/o 33v 4/8/1?/16 ?a pa ? 4 4 4 3 pa3 ai/o 33v 4/8/1?/16 ?a pa3 5 5 5 4 pa4 ai/o 33v 4/8/1?/16 ?a pa4 6 6 6 5 pa5 ai/o 33v 4/8/1?/16 ?a pa5 ? ? ? 6 pa6 ai/o 33v 4/8/1?/16 ?a pa6 8 8 8 ? pa ? ai/o 33v 4/8/1?/16 ?a pa ? 9 pe8 ai/o 33v 4/8/1?/16 ?a pe8 10 pe9 ai/o 33v 4/8/1?/16 ?a pe9 11 pe10 ai/o 33v 4/8/1?/16 ?a pe10 1? pe11 ai/o 33v 4/8/1?/16 ?a pe11 13 pe1? ai/o 33v 4/8/1?/16 ?a pe1? 14 9 9 vdd_3 p voltage fo ? digital i/o 15 10 10 ep vss_3 p g?ound ?efe?ence fo? digital i/o 16 11 pc9 ai/o 33v 4/8/1?/16 ?a pc9 1? 1? pc10 ai/o 33v 4/8/1?/16 ?a pc10 18 13 pc11 ai/o 33v 4/8/1?/16 ?a pc11 19 14 pc1? ai/o 33v 4/8/1?/16 ?a pc1? ?0 pd6 ai/o 33v 4/8/1?/16 ?a pd6 ?1 15 11 8 pb1? i/o 33v 4/8/1?/16 ?a pb1? ?? 15 11 8 usbdm ai/o usb diffe ?ential data ?us confo??ing to the unive?sal se?ial bus standa?d ?3 16 1? 9 usbdp ai/o usb diffe ?ential data ?us confo??ing to the unive?sal se?ial bus standa?d ?4 16 1? 9 pb13 i/o 33v 4/8/1?/16 ?a pc? ?5 ?c ?c ?6 1? 13 10 cldo p co?e powe? ldo 1.5v output. it is ?eco??ended to connect a 4.?uf capacito? as close as possi?le ?etween this pin and vss_1. ?? 18 14 11 vdd_1 p voltage fo ? digital i/o ?8 19 15 1? vss_1 p g?ound ?efe?ence fo? digital i/o ?9 ?0 16 13 nrst i(bk) 33v_pu exte?nal ?eset pin and exte?nal wakeup pin in the powe?-down ?ode 30 ?1 1? 14 vbat p batte?y powe? input fo? the ?ackup do?ain 31 ?? 18 15 pc13(4) ai/ o(bk) 33v < ? ?a x3?ki? 3? ?3 19 16 pc14(4) ai/ o(bk) 33v < ? ?a x3?kout 33 ?4 ?0 1? pc15(4) i/ o(bk) 33v < ? ?a rtcout 34 ?5 pd0 i/o 33v 4/8/1?/16 ?a pd0 35 pe13 i/o 33v 4/8/1?/16 ?a pe13 36 pe14 i/o 33v 4/8/1?/16 ?a pe14 3? pe15 i/o 33v 4/8/1?/16 ?a pe15 rev. 1.00 3? of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 pin assignment pin number pin name type (1) i/o structure (2) output driving description 100 lqfp 64 lqfp 48 lqfp 46 qfn default function (af0) 38 ?6 ?1 18 pb14 ai/o 33v 4/8/1?/16 ?a xtali ? 39 ?? ?? 19 pb15 ai/o 33v 4/8/1?/16 ?a xtalout 40 vdd_5 p voltage fo ? digital i/o 41 vss_5 p g?ound ?efe?ence fo? digital i/o 4? pd1 i/o 33v 4/8/1?/16 ?a pd1 43 pd? i/o 33v 4/8/1?/16 ?a pd? 44 pd3 i/o 33v 4/8/1?/16 ?a pd3 45 ?8 ?3 ?0 pd4 i/o 33v 4/8/1?/16 ?a pd4 46 ?9 ?4 ?1 pd5 i/o 33v 4/8/1?/16 ?a pd5 4? 30 pc0 i/o 33v 4/8/1?/16 ?a pc0 48 31 pc1 i/o 33v 4/8/1?/16 ?a pc1 49 3? pc? i/o 33v 4/8/1?/16 ?a pc? 50 33 pc3 i/o 33v 4/8/1?/16 ?a pc3 51 pd? i/o 33v 4/8/1?/16 ?a pd? 5? pd8 i/o 33v 4/8/1?/16 ?a pd8 53 34 ?5 ?? pa8 i/o 33v_pu 4/8/1?/16 ?a pa8_boot0 54 35 ?6 ?3 pa9 i/o 33v_pu 4/8/1?/16 ?a pa9_boot1 55 36 ?? ?4 pa10 i/o 33v 4/8/1?/16 ?a pa10 56 3? ?8 ?5 pa11 i/o 33v 4/8/1?/16 ?a jtdo 5? 38 ?9 ?6 pa1 ? i/o 33v_pu 4/8/1?/16 ?a jtck/swclk 58 39 30 ?? pa13 i/o 33v_pu 4/8/1?/16 ?a jtms/swdio 59 40 31 ?8 pa14 i/o 33v_pu 4/8/1?/16 ?a jtdi 60 41 3? ?9 pa15 i/o 33v_pu 4/8/1?/16 ?a jtrst 61 4? vdd_? p voltage fo ? digital i/o 6? 43 vss_? p g?ound ?efe?ence fo? digital i/o 63 44 33 30 pb0 i/o 33v 4/8/1?/16 ?a pb0 64 45 34 31 pb1 i/o 33v 4/8/1?/16 ?a pb1 65 46 pc4 i/o 33v 4/8/1?/16 ?a pc4 66 4? pc5 i/o 33v 4/8/1?/16 ?a pc5 6? 48 pc6 i/o 33v 4/8/1?/16 ?a pc6 68 pd9 i/o 33v 4/8/1?/16 ?a pd9 69 pd10 i/o 33v 4/8/1?/16 ?a pd10 ?0 pd11 i/o 33v 4/8/1?/16 ?a pd11 ?1 pd1? i/o 33v 4/8/1?/16 ?a pd1? ?? pd13 i/o 33v 4/8/1?/16 ?a pd13 ?3 pd14 i/o 33v 4/8/1?/16 ?a pd14 ?4 pd15 i/o 33v 4/8/1?/16 ?a pd15 ?5 pe0 i/o 33v 4/8/1?/16 ?a pe0 35 3? vdd_? p voltage fo ? digital i/o 36 33 vss_? p g?ound ?efe?ence fo? digital i/o ?6 49 3? 34 pb? i/o 33v 4/8/1?/16 ?a pb? ?? 50 38 35 pb3 i/o 33v 4/8/1?/16 ?a pb3 ?8 51 39 36 pb4 i/o 33v 4/8/1?/16 ?a pb4 ?9 5? 40 3? pb5 i/o 33v 4/8/1?/16 ?a pb5 rev. 1.00 33 of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 pin assignment pin assignment pin number pin name type (1) i/o structure (2) output driving description 100 lqfp 64 lqfp 48 lqfp 46 qfn default function (af0) 80 53 pc? i/o 33v 4/8/1?/16 ?a pc? 81 54 pc8 i/o 33v 4/8/1?/16 ?a pc8 8? pe1 i/o 33v 4/8/1?/16 ?a pe1 83 pe? i/o 33v 4/8/1?/16 ?a pe? 84 pe3 i/o 33v 4/8/1?/16 ?a pe3 85 55 vdd_4 p voltage fo ? digital i/o 86 56 vss_4 p g?ound ?efe?ence fo? digital i/o 8? pe4 i/o 33v 4/8/1?/16 ?a pe4 88 pe5 i/o 33v 4/8/1?/16 ?a pe5 89 pe6 i/o 33v 4/8/1?/16 ?a pe6 90 pe? i/o 33v 4/8/1?/16 ?a pe? 91 5? 41 38 pb6 ai/o 33v 4/8/1?/16 ?a pb6 9? 58 4? 39 pb? ai/o 33v 4/8/1?/16 ?a pb? 93 59 43 40 pb8 ai/o 33v 4/8/1?/16 ?a pb8 94 60 44 41 pb9 ai/o 33v 4/8/1?/16 ?a pb9 95 61 45 4? pb10 ai/o 33v 4/8/1?/16 ?a pb10 96 6? 46 43 pb11 ai/o 33v 4/8/1?/16 ?a pb11 9? 63 4? 44 vdda p analog voltage fo? adc and co?pa?ato? 98 63 4? 44 vref+ p adc positive ?efe?ence voltage has to ?e lowe? o? equal to v dda 99 64 48 45 vref- p adc negative ?efe?ence voltage has to ?e di?ectly connected to vssa 100 64 48 45 vssa p g?ound ?efe?ence fo? the adc and co?pa?ato? ?ote: 1. i = input? o = output? a = analog po?t? p = powe? supply ? pu = pull-up? bk = backup do?ain? ep = exposed pad of the qf? package. ?. 33 v = 3.3 v tole?ant. 3. the gpios a ? e in an af0 state afte? a v dd15 powe ? on ? eset (por) except fo? the rtcout pin in the backup do? ain i/o. the rtcout pin is ?eset ?y the backup do? ain powe?-on-? eset (porb) o? ?y the backup do?ain softwa?e ? eset (bak_rst ?it in bak_cr ?egiste?). 4. the ?ackup do? ain of the i/o pins have a sou?ce cu??ent capa? ility li?itation of < ? ? a @ v dd = 3.3 v and sink current typical is 4/8 ma confgurable @ v dd = 3.3 v. rev. 1.00 34 of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 electrical characteristics 5 electrical characteristics absolute maximum ratings the following table shows the absolute maximum ratings of the device. these are stress ratings only. stresses beyond absolute maximum ratings may cause permanent damage to the device. note that the device is not guaranteed to operate properly at the maximum ratings. exposure to the absolute maximum rating conditions for extended periods may affect device reliability. table 5. absolute maximum ratings symbol parameter min. max. unit. v dd exte?nal ?ain supply voltage v ss - 0.3 v ss + 3.6 v v dda exte?nal analog supply voltage v ssa - 0.3 v ssa + 3.6 v v bat exte?nal ?atte?y supply voltage v ss - 0.3 v ss + 3.6 v v i? input voltage on othe? i/o v ss - 0.3 v dd + 0.3 v t a a??ient ope?ating te?pe?atu?e ?ange -40 85 c t stg sto?age te?pe?atu?e ?ange -55 150 c t j maxi?u? junction te?pe?atu?e 1?5 c p d total powe ? dissipation 500 ?w v esd elect?ostatic discha?ge voltage C hu?an ?ody ?ode -4000 4000 v recommended dc operating conditions table 6. recommended dc operating conditions t a = ?5 c , unless otherwise specifed. symbol parameter conditions min. typ. max. unit v dd i/o ope?ating voltage ?.0 3.3 3.6 v v dda analog ope?ating voltage ?.5 3.3 3.6 v v bat batte?y supply ope?ating voltage ?.0 3.3 3.6 v on-chip ldo voltage regulator characteristics table 7. ldo characteristics t a = ?5 c , unless otherwise specifed. symbol parameter conditions min. typ. max. unit v ldo inte?nal ?egulato? output voltage v dd ?.0 v regulato? input @ i ldo = 35 ? a and voltage va?iant = 5%? afte? t?i??ing 1.4?5 1.5 1.5? v i ldo output cu??ent v dd = ?.0 v regulato? input @ v ldo = 1.5 v 50 ?5 ?a c ldo external flter capacitor value fo? inte?nal co?e powe? supply the capacito? value is dependent on the co?e powe? cu??ent consu?ption ?.? 4.? f rev. 1.00 35 of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 electrical characteristics electrical characteristics power consumption table 8. power consumption characteristics t a = ?5 c , unless otherwise specifed. symbol parameter f hclk conditions min . typ . max . unit i dd supply cu??ent (run ?ode) 96 mhz v dd = v bat = 3.3 v hsi = 8 mhz pll = 96 mhz all pe?iphe?als ena?led 51 ?a all pe?iphe?als disa?led ?8 ?? mhz v dd = v bat = 3.3 v hsi = 8 mhz pll = ?? mhz all pe?iphe?als ena?led 4?.5 all pe?iphe?als disa?led ?4 48 mhz v dd = v bat = 3.3 v hsi = 8 mhz pll = 96 mhz all pe?iphe?als ena?led 3? all pe?iphe?als disa?led ?0 ?4 mhz v dd = v bat = 3.3 v hsi = 8 mhz pll = 96 mhz all pe?iphe?als ena?led ?1.5 all pe?iphe?als disa?led 1? 8 mhz v dd = v bat = 3.3 v hsi = 8 mhz pll = off all pe?iphe?als ena?led 10.5 all pe?iphe?als disa?led 5.6 1 mhz v dd = v bat = 3.3 v hsi = 8 mhz pll = off all pe?iphe?als ena?led 4.8 all pe?iphe?als disa?led ?.? 3? khz v dd = v bat = 3.3 v lsi = 3? khz ldo low cu??ent ?ode all pe?iphe?als ena?led 61 a all pe?iphe?als disa?led 50 supply cu??ent (sleep ?ode) 96 mhz v dd = v bat = 3.3 v hsi = 8 mhz pll = 96 mhz mcu co?e sleep all pe?iphe?als ena?led 30 ?a all pe?iphe?als disa?led 3.? supply cu??ent (deep-sleep1 ?ode) v dd = v bat = 3.3 v ? all clock off (hsi/pll/f hclk )? ldo in low powe? ?ode? lse off? lsi on? rtc on 35 a supply cu??ent (deep - sleep? ?ode) v dd = v bat = 3.3 v ? all clock off (hsi/pll/f hclk )? ldo off (dmos on) ? lse off? lsi on? rtc on 14 a supply cu??ent (powe? - down ?ode) v dd = v bat = 3.3v ? ldo off? lse on? lsi on? rtc on 1.9 a v dd = v bat = 3.3 v ? ldo off? lse off? lsi on? rtc off 1.? a i bat batte?y supply cu??ent (powe? - down ?ode) v dd not p?esent? v bat = 3.3 v ? ldo off? lse on? lsi on? rtc on ?.4 a v dd not p?esent? v bat = 3.3 v ? ldo off? lse off ? lsi on? rtc off 1.5 a ?ote: 1. hse ?eans high speed exte?nal oscillato? . hsi ?eans 8 mhz high speed inte?nal oscillato? . ?. lse ?eans 3?.?68 khz low speed exte?nal oscillato? . lsi ?eans 3? khz low speed inte?nal oscillato? . 3. rtc ?eans ?eal ti?e clock. 4. code = while (1) { ?08 ? op } executed in flash. rev. 1.00 36 of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 electrical characteristics reset and supply monitor characteristics table 9. v dd power reset characteristics t a = ?5 c , unless otherwise specifed. symbol parameter conditions min. typ. max. unit v por powe? on ?eset th?eshold (rising voltage on v dd ) t a = -40 c ~ 85 c 1.66 1.?9 1.90 v v pdr powe? down ?eset th?eshold (falling voltage on v dd ) 1.49 1.64 1.?8 v v porhyst por hyste?esis 150 ?v t por reset delay ti?e v dd = 3.3 v 0.1 0.? ?s ?ote: 1. data ?ased on cha?acte?ization ?esults only ? not tested in p?oduction. ?. gua?anteed ?y design? not tested in p?oduction. 3. if the ldo will ?e tu?n on? the vdd por has to ?e in the de-asse? tion condition. when the vdd por is in the asse?tion state then the ldo will ?e tu? n off. table 10. lvd/bod characteristics t a = ?5 c , unless otherwise specifed. symbol parameter conditions min. typ. max. unit v bod voltage of b ?own out detection t a = -40 c ~ 85 c afte? facto?y-t?i??ed (v dd falling edge) ?.0? ?.1 ?.18 v v lvd voltage of low voltage detection t a = -40 c ~ 85 c (v dd falling edge) lvds = 000 ?.1? ?.?5 ?.33 v lvds = 001 ?.3? ?.4 ?.48 v lvds = 010 ?.4? ?.55 ?.63 v lvds = 011 ?.6? ?.? ?.?8 v lvds = 100 ?.?? ?.85 ?.93 v lvds = 101 ?.9? 3.0 3.08 v lvds = 110 3.0? 3.15 3.?3 v lvds = 111 3.?? 3.3 3.38 v v lvdhtst lvd hyste ?esis v dd = 3.3 v 100 ?v t su lvd lvd setup ti ?e v dd = 3.3 v 5 s t atlvd lvd active delay ti ?e v dd = 3.3 v s i ddlvd ope?ation cu??ent ( 3 ) v dd = 3.3 v 5 15 a ?ote: 1. data ?ased on cha?acte?ization ?esults only ? not tested in p?oduction. ?. gua?anteed ?y design? not tested in p?oduction. 3. bandgap cu??ent is not included. 4. lvds feld is in pwrcu lvdcsr register. rev. 1.00 3? of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 electrical characteristics electrical characteristics external clock characteristics table 11. high speed external clock (hse) characteristics t a = ?5 c , unless otherwise specifed. symbol parameter conditions min. typ. max. unit v dd ope?ation range ?.0 3.6 v f hse high speed exte?nal oscillato? f?equency (hse) 4 16 mhz c lhse load capacitance v dd = 3.3 v ? r esr = 100 @ 16 mhz ?? pf r fhse inte?nal feed?ack ?esisto? ?etween xtali ? and xtalout pins v dd = 3.3 v 1 m r esr equivalent se?ies resistance v dd = 3.3 v ? c l = 1? pf @ 16 mhz? hsedr = 0 100 v dd = ?.4 v ? c l = 1? pf @ 16 mhz? hsedr = 1 ?00 d hse hse oscillato? duty cycle 40 60 % i ddhse hse oscillato? cu??ent consu?ption v dd = 3.3 v c l = 1? pf hsedr = 0 8 mhz 0.?5 ?a 16 mhz 1 i pwdhse hse oscillato? powe? down cu??ent v dd = 3.3 v 0.01 a t suhse hse oscillato? sta?tup ti?e v dd = 3.3 v @ 8 mhz? hsedr = 0 4 ?s table 12. low speed external clock (lse) characteristics t a = ?5 c , unless otherwise specifed. symbol parameter conditions min. typ. max. unit v bak ope?ation range ?.0 3.6 v f ck_lse f?equency of lse v bak = ?.0 v ~ 3.6 v 3?.?68 khz r f inte?nal feed?ack ?esisto? 10 m? r esr equivalent se?ies resistance v bak = 3.3 v 30 tbd k? c l reco??ended load capacitances v bak = 3.3 v 6 tbd pf i ddlse oscillato? supply cu??ent (high cu??ent ?ode) f ck_lse = 3?.?68 khz? r esr = 50 k?, c l >= ? pf v bak = ?.0 v ~ ?.? v ? t a = -40 c ~ 85 c 3.3 6.3 a oscillato? supply cu??ent (low cu??ent ?ode) f ck_lse = 3?.?68 khz? r esr = 50 k?, c l < ? pf v bak = ?.0 v ~ 3.6 v ? t a = -40 c ~ 85 c 1.8 3.3 a powe? down cu??ent 0.01 a t su lse sta?tup ti?e (low cu??ent ?ode) f ck_ls e = 3?.?68 khz? v bak = ?.? v ~ 3.6 v ?.5 s ?ote : the following guidelines a ?e ?eco?? ended to inc? ease the ?o? ustness of the c?ystal ci?cuit of the hse / lse clock in the pcb layout phase . 1. the c ? ystal oscillato? should ? e located as close as possi? le to the mcu so that the t ? ace length would ?e as sho?t as possi?le to ?educe the pa?asitic capacitance. rev. 1.00 38 of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 electrical characteristics ? . shield lines in the vicinity of the c? ystal ? y using a g? ound plane to isolate signals and ?educe noise. 3. keep the f ? equently switching signal lines away f ? o? the c ? ystal a ? ea to p ? event the c?osstalk. internal clock characteristics table 13. high speed internal clock (hsi) characteristics t a = ?5 c , unless otherwise specifed. symbol parameter conditions min. typ. max. unit v dd ope?ation range ?.0 3.6 v f hsi f?equency of hsi v dd = 3.3 v @ ?5 c 8 mhz acc hsi f?equency accu?acy of the facto?y-cali??ated hsi oscillato? v dd = 3.3 v ? t a = ?5 c -? ? % v dd = ?.5 v ~ 3.6 v ? t a = -40 c ~ 85 c -3 3 % v dd = ?.0 v ~ 3.6 v t a = -40 c ~ 85 c -4 4 % duty duty cycle f hsi = 8 mhz 35 65 % i ddhsi oscillato? supply cu??ent f hsi = 8 mhz ??0 ?50 a powe? down cu??ent 0.05 a t su hsi sta?tup ti?e f hsi = 8 mhz 10 s table 14. low speed internal clock (lsi) characteristics t a = ?5 c , unless otherwise specifed. symbol parameter conditions min. typ. max. unit f lsi low speed inte?nal oscillato? f?equency (lsi) v bak = 3.3 v ? t a = -40 c ~ 85 c ?1 3? 43 khz acc lsi f?equency accu?acy of lsi afte? facto?y-t?i??ed? v bak = 3.3 v ? t a = ?5 c -10 +10 % i ddlsi lsi oscillato? ope?ating cu??ent v bak = 3.3 v ? t a = ?5 c 0.8 1.? a t sulsi lsi oscillato? sta?tup ti?e v bak = 3.3 v ? t a = ?5 c 100 s pll characteristics table 15. pll characteristics t a = ?5 c , unless otherwise specifed. symbol parameter conditions min. typ. max. unit f plli? pll input clock 4 16 mhz f ck_pll pll output clock 64 96 mhz t lock pll lock ti ?e ?00 s rev. 1.00 39 of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 electrical characteristics electrical characteristics usb pll characteristics table 16. usb pll characteristics t a = ?5 c , unless otherwise specifed. symbol parameter conditions min. typ. max. unit f plli? pll input clock 4 16 mhz f ck_pll pll output clock 16 48 mhz t lock pll lock ti ?e ?00 s memory characteristics table 17. flash memory characteristics t a = ?5 c , unless otherwise specifed. symbol parameter conditions min. typ. max. unit ? e?du ?u??e? of gua?anteed p?og?a?/ e?ase cycles ?efo?e failu?e (endu?ance) t a = -40 c ~ 85 c 10 k cycles t ret data ?etention ti?e t a = -40 c ~ 85 c 10 yea ?s t prog wo ?d p?og?a??ing ti?e t a = -40 c ~ 85 c ?0 s t erase page e?ase ti?e t a = -40 c ~ 85 c ? ?s t merase mass e?ase ti?e t a = -40 c ~ 85 c 10 ?s i/o port characteristics table 18. i/o port characteristics t a = ?5 c , unless otherwise specifed. symbol parameter conditions min. typ. max. unit i il low level input cu??ent 3.3 v i/o v i = v ss ? on-chip pull- up ?esiste? disa?led 3 a reset pin 3 a i ih high level input cu??ent 3.3 v i/o v i = v dd? on-chip pull- down ?esiste? disa?led 3 a reset pin 3 a v il low level input voltage 3.3 v i/o -0.5 0.35 v dd v reset pin -0.5 0.35 v dd v v ih high level input voltage 3.3 v i/o 0.65 v dd v dd + 0.5 v reset pin 0.65 v dd v dd + 0.5 v v hys sch?itt t?igge? input voltage hyste?esis 3.3 v i/o 0.1? v dd ?v reset pin 0.1? v dd ?v rev. 1.00 40 of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 electrical characteristics symbol parameter conditions min. typ. max. unit i ol low level output cu??ent (gpio sink cu??ent) 3.3 v i/o 4 ? a d?ive? v ol = 0.4 v 4 ?a 3.3 v i/o 8 ? a d?ive? v ol = 0.4 v 8 ?a 3.3 v i/o 1? ? a d?ive? v ol = 0.4 v 1? ?a 3.3 v i/o 16 ? a d?ive? v ol = 0.4 v 16 ?a backup do?ain i/o d?ive @ v dd = 3.3 v ? v ol = 0.4 v ? pb10? pb11? pb1? 4 ?a i oh high level output cu??ent (gpio sou?ce cu??ent) 3.3 v i/o 4 ? a d?ive? v oh = v dd - 0.4 v 4 ?a 3.3 v i/o 8 ? a d?ive? v oh = v dd - 0.4 v 8 ?a 3.3 v i/o 1? ? a d?ive? v oh = v dd - 0.4 v 1? ?a 3.3 v i/o 16 ? a d?ive? v oh = v dd - 0.4 v 16 ?a backup do?ain i/o d?ive @ v dd = 3.3 v ? v ol = v dd - 0.4 v ? pb10? pb11? pb1?. ? ?a v ol low level output voltage 3.3v 4 ? a d?ive i/o? i ol = 4 ?a 0.4 v 3.3v 8 ? a d?ive i/o? i ol = 8 ?a 0.4 v 3.3v 1? ? a d?ive i/o? i ol = 1? ?a 0.4 v 3.3v 16 ? a d?ive i/o? i ol = 16 ?a 0.4 v backup do?ain i/osink cu??ent = 4 ? a (low d?iving st?ength) v dd = ?.? v ~ 3.6 v 0.4 v v dd = ?.0 v ~ ?.? v 0.6 v backup do?ain i/o sink cu??ent = 8 ? a (high d?iving st?ength) v dd = ?.? v ~ 3.6 v 0.4 v v dd = ?.0 v~ ?.? v 0.6 v v oh high level output voltage 3.3 v 4 ? a d?ive i/o? i oh = 4 ?a v dd - 0.4 v 3.3 v 8 ? a d?ive i/o? i oh = 8 ?a v dd - 0.4 v 3.3 v 1? ? a d?ive i/o? i ol = 1? ?a v dd - 0.4 v 3.3 v 16 ? a d?ive i/o? i ol = 16 ?a v dd - 0.4 v backup do?ain i/ o sou?ce cu??ent = ? ?a v dd = ?.? v ~ 3.6 v ?.4 v backup do?ain i/ o sou?ce cu??ent = 1 ?a v dd = ?.0 v ~ ?.? v v dd - 0.4 v r pu inte?nal pull-up ?esisto? 3.3 v i/o 46 k r pd inte?nal pull-down ?esisto? 3.3 v i/o 46 k rev. 1.00 41 of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 electrical characteristics electrical characteristics adc characteristics table 19. adc characteristics t a = ?5 c , unless otherwise specifed. symbol parameter conditions min. typ. max. unit v dda ope?ating voltage ?.5 3.3 3.6 v v adci? a/d conve?te? input voltage ?ange 0 v ref+ v v ref+ a/d conve?te? refe?ence voltage v dda v dda v i adc cu??ent consu?ption v dda = 3.3 v 0.85 1 ?a i adc_d? powe? down cu??ent consu?ption v dda = 3.3 v 0.1 a f adc a/d conve?te? clock 0.? 16 mhz f s sa?pling ?ate 0.05 1 mhz t dl data latency 1?.5 1/f adc cycles t s&h sa?pling & hold ti?e 3.5 1/f adc cycles t adcco?v a/d conve?te? conve?sion ti?e 16 1/f adc cycles r i input sa?pling switch ?esistance 1 k c i input sa?pling capacitance ?o pin/pad capacitance included 16 pf t su sta?tup up ti?e 1 s ? resolution 1? ?its i?l integ?al ?on-linea?ity e??o? f s = ?50 khz? v dda = 3.3 v ? 5 lsb d?l diffe ?ential ?on-linea?ity e??o? f s = ?50 khz? v dda = 3.3 v 1 lsb e o offset e ??o? 10 lsb e g gain e??o? 10 lsb ?ote: 1. gua?anteed ?y design? not tested in p?oduction. 2. the fgure below shows the equivalent circuit of the a/d converter sample-and-hold input stage whe?e c i is the sto?age capacito ?? r i is the ? esistance of the sa? pling switch and r s is the output i ? pedance of the signal sou? ce v s . ?o?? ally the sa? pling phase du? ation is app?oxi?ately ? 3.5/f adc . the capacitance ? c i ? ? ust ?e cha? ged within this ti?e f?a? e and it ?ust ? e ensu? ed that the voltage at its te??inals ?eco? es sufficiently close to v s fo ? accu? acy. to gua?antee this? r s ?ay not have an a??it?a?ily la?ge value. rev. 1.00 4? of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 electrical characteristics sar adc c i sa?ple r i r s v s figure 8. adc sampling network model the worst case occurs when the extremities of the input range (0 v and v ref ) are sampled consecutively. in this situation a sampling error below 1/4 lsb is ensured by using the following equation: r s < f adc c i ln(2 n+2 ) 3.5 C r i where f adc is the adc clock frequency and n is the adc resolution (n = 12 in this case). a safe margin should be considered due to the pin/pad parasitic capacitances, which are not accounted for in this simple model. if, in a system where the a/d converter is used, there are no rail-to-rail input voltage variations between consecutive sampling phases, r s may be larger than the value indicated by the equation above. comparator characteristics table 20. comparator characteristics t a = ?5 c , unless otherwise specifed. symbol parameter conditions min. typ. max. unit v dda ope?ating voltage co?pa?ato? ?ode ?.5 3.3 3.6 v v i? input co??on mode voltage range cp o ? c? v ssa v dda v v ios input offset voltage (1) t a = ?5 c -15 15 ?v v hys input hyste?esis ?o hyste?esis (cmpnhm[1:0] = 00) low speed 0 ?v high speed 0 low hyste?esis (cmpnhm[1:0] = 01) low speed 30 ?v high speed 30 middle hyste?esis (cmpnhm[1:0] = 10) low speed 50 ?v high speed ?0 high hyste?esis (cmpnhm[1:0] = 11) low speed ?0 ?v high speed 100 rev. 1.00 43 of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 electrical characteristics electrical characteristics symbol parameter conditions min. typ. max. unit t rt response ti?e input ove?d?ive = 100?v high speed ?ode v dda 2.7 v 50 100 ns v dda < ?.? v 100 ?50 low speed ?ode ? 5 s i cmp cu??ent consu?ption v dda = 3.3 v high speed ?ode 180 a low speed ?ode 30 a t cmpst co?pa?ato? sta? tup ti?e co?pa?ato? ena?led to output valid 50 s i cmp_d? powe? down supply cu??ent cmpe? = 0 ? cvrefe? = 0 ? cvrefoe = 0 0.1 a comparator voltage reference (cvr) v cvr output range v ssa v dda v ? bits cvr scale? resolution 6 ?its t cvrst setting ti ?e cvr scale? setting ti?e f?o? cvref = 000000 to 111111 100 s i cvr cu??ent consu?ption v dda = 3.3 v cvrefe? = 1? cmprefoe = 0 65 a cvrefe? = 1? cvrefoe = 1 80 110 a ?ote: gua?anteed ?y design? not tested in p?oduction. gptm/mctm characteristics table 21. gptm/mctm characteristics symbol parameter conditions min. typ. max. unit f tm ti ?e? clock sou?ce fo? gptm and mctm 96 mhz t res ti ?e? ?esolution ti?e 1 f tm f ext exte?nal single f?equency on channel 1 ~ 4 1/? f tm res ti ?e? ?esolution 16 ?its i 2 c characteristics table 22. i 2 c characteristics symbol parameter standard mode fast mode fast mode plus unit min. max. min. max. min. max. f scl scl clock f ?equency 100 400 1000 khz t scl(h) scl clock high ti ?e 4.5 1.1?5 0.45 s t scl(l) scl clock low ti ?e 4.5 1.1?5 0.45 s t fall scl and sda fall ti ?e 1.3 0.34 0.135 s t rise scl and sda ?ise ti?e 1.3 0.34 0.135 s t su(sda) sda data setup ti ?e 500 1?5 50 ns t h(sda) sda data hold ti ?e 0 0 0 ns rev. 1.00 44 of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 electrical characteristics symbol parameter standard mode fast mode fast mode plus unit min. max. min. max. min. max. t su(sta) start condition setup ti?e 500 1?5 50 ns t h(sta) start condition hold ti ?e 0 0 0 ns t su(sto) stop condition setup ti ?e 500 1?5 50 ns ?ote: 1. gua?anteed ?y design? not tested in p?oduction. ? . to achieve 100 khz standa?d ?ode? the pe?iphe?al clock f?equency ?ust ?e highe? than ? mhz. 3. to achieve 400 khz fast ?ode? the pe?iphe?al clock f?equency ?ust ?e highe? than 8 mhz. 4. to achieve 1 mhz fast ?ode plus? the pe?iphe?al clock f?equency ?ust ?e highe? than ?0 mhz. 5. the a ? ove cha?acte? istic pa?a?ete? s of the i ? c ? us ti? ing a?e ? ased on: seq_filter = 01 and comb_filter_en is disa ?led. t su(sta) t h(sta) t fall t scl(l) t rise t scl(h) t h(sda) t su(sda) t su(sto) scl sda figure 9. i 2 c timing diagrams spi characteristics table 23. spi characteristics symbol parameter conditions min. typ. max. unit spi master mode f sck (1/t sck ) spi ?aste? output sck clock f?equency maste? ?odespi pe?iphe?al clock f?equency f pclk f pclk /? mhz t sck(h) t sck(l) sck clock high and low ti?e t sck / ? - ? t sck /? + 1 ns t v(mo) data output valid ti?e 5 ns t h(mo) data output hold ti?e ? ns t su(mi) data input setup ti?e 5 ns t h(mi) data input hold ti?e 5 ns spi slave mode f sck (1/t sck ) spi slave input sck clock f?equency slave ?ode spi pe?iphe?al clock f?equency f pclk f pclk /3 mhz duty sck spi slave input sck clock duty cycle 30 ?0 % t su(sel) sel ena ?le setup ti?e 3 t pclk ns t h(sel) sel ena ?le hold ti?e ? t pclk ns rev. 1.00 45 of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 electrical characteristics electrical characteristics symbol parameter conditions min. typ. max. unit t a(so) data output access ti?e 3 t pclk ns t dis(so) data output disa?le ti?e 10 ns t v(so) data output valid ti?e ?5 ns t h(so) data output hold ti?e 15 ns t su(si) data input setup ti?e 5 ns t h(si) data input hold ti?e 4 ns ?ote: t sck = 1/f sck ; t pclk = 1/f pclk . spi output (input) clock f?equency f sck ; spi pe?iphe?al clock f? equency f pclk . sck(cpol=0) sck(cpol=1) mosi miso mosi miso t sck t sck(h) t sck(l) data valid data valid data valid t su(mi) t v(mo) t h(mo) t h(mi) data valid data valid data valid t v(mo) t h(mo) data valid data valid data valid data valid data valid data valid t su(mi) t h(mi) cpha=1 cpha=0 figure 10. spi timing diagrams C spi master mode rev. 1.00 46 of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 electrical characteristics sck(cpol=0) sck(cpol=1) mosi miso t sck t sck(h) t sck(l) msb/lsb i? t h(si) t su(sel) t h(sel) t su(si) lsb/msb i? msb/lsb out lsb/msb out t a(so) t v(so) t h(so) t dis(so) sel figure 11. spi timing diagrams C spi slave mode with cpha=1 i 2 s characteristics table 24. i 2 s characteristics symbol parameter conditions min. typ. max. unit i 2 s master mode t wsd(mo) ws output to bclk delay 0 4.6 ns t dod(mo) data output to bclk delay 0.5 5.4 ns t dis(mi) data input setup ti?e 0 ns t dih(mi) data input hold ti?e 13 ns i 2 s slave mode t bch(si) bclk high pulse width 4? ns t bcl(si) bclk low pulse width 4? ns t wss(si) ws input setup ti?e 0 ns t dod(so) data output to bclk delay 9 ns t dis(si) data input setup ti?e 0 ns t dih(si) data input hold ti?e ?.1 ns ?ote: 1. gua?anteed ?y cha?acte?ization ?esults? not tested in p?oduction. ?. i/o d?iving cu??ent is set to 4 ?a. 3. capacitive load c = 10 pf ? v dd = 3.3 v and a??ient te?pe?atu? e t a = ?5 c. 4. measu?e?ent points a?e set at cmos levels = 0.5 v dd . rev. 1.00 4? of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 electrical characteristics electrical characteristics bclk ws sdo sdi t dis(mi) t dih(mi) t dod(mo) t wsd(mo) figure 12. timing of i 2 s master mode bclk ws sdo sdi t dis(si) t dih(si) t dod(so) t wss(si) t bch(si) t bcl(si) figure 13. timing of i 2 s slave mode rev. 1.00 48 of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 electrical characteristics sdio characteristics table 25. sdio characteristics symbol parameter conditions min. typ. max. unit f sdck clock f?equency in data t?ansfe? ?ode 48 mhz t w(ckl) clock low ti?e f sdck = 48 mhz 9 ns t w(ckh) clock high ti?e f sdck = 48 mhz 10 ns cmd, data inputs referenced to sd_clk in sd default mode t isu(sd) input setup ti?e sd default ?ode f sdck = ?4 mhz 3 ns t ih(sd) input hold ti?e sd default ?ode f sdck = ?4 mhz 0 ns cmd, data outputs referenced to sd_clk in sd default mode t ov(sd) output valid ti?e sd default ?ode f sdck = ?4 mhz 5 ? ns t oh(sd) output hold ti?e sd default ?ode f sdck = ?4 mhz ? ns cmd, data inputs referenced to sd_clk in sd hs mode t isu(hs) input setup ti?e sd hs ?ode f sdck = 48 mhz ? ns t ih(hs) input hold ti?e sd hs ?ode f sdck = 48 mhz 0.5 ns cmd, data outputs referenced to sd_clk in sd hs mode t ov(hs) output valid ti?e sd hs ?ode f sdck = 48 mhz 6.5 8 ns t oh(hs) output hold ti?e sd hs ?ode f sdck = 48 mhz 1.5 ns ?ote: 1. gua?anteed ?y cha?acte?ization ?esults? not tested in p?oduction. ?. i / o d?iving cu??ent is set to 16 ?a. 3. capacitive load c = 30 pf ? v dd = 3.3 v and a??ient te?pe?atu? e t a = ?5 c . 4. measu?e?ent points a?e set at cmos levels = 0.5 v dd. sd_clk cmd & dat (output) t ih(sd) t ov(sd) cmd & dat (input) t oh(sd) t isu(sd) figure 14. sdio default mode rev. 1.00 49 of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 electrical characteristics electrical characteristics sd_clk cmd & dat (output) t ih(hs) t ov(hs) cmd & dat (input) t oh(hs) t isu(hs) figure 15. sdio high-speed mode csif characteristics table 26. csif electrical characteristics symbol parameter conditions min. typ. max. unit f mck csif_mck clock f?equency output 48 mhz f pck csif_pck clock f?equency input 3? mhz ? f ahb clock and csif_pck clock input f?equency ?atio f pclk /f csif_pck 3 usb characteristics the usb interface is usb-if certifed C full speed. table 27. usb dc electrical characteristics symbol parameter conditions min. typ. max. unit v dd usb ope?ating voltage 3.0 3.6 v v di diffe ?ential input sensitivity |usbdp C usbdm| 0.? v v cm co??on ?ode voltage ?ange 0.8 ?.5 v v se single-ended ?eceive? th?eshold 0.8 ?.0 v v ol pad output low voltage r l of 1.5 k to v dd 0 0.3 v v oh pad output high voltage ?.8 3.6 v v crs diffe ?ential output signal c?oss-point voltage 1.3 ?.0 v z drv d?ive? output ?esistance 10 rev. 1.00 50 of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 electrical characteristics symbol parameter conditions min. typ. max. unit c i? t ?ansceive? pad capacitance ?0 pf ?ote: 1. gua?anteed ?y design? not tested in p?oduction. ? . the usb functionality is ensu?ed down to ?.? v ?ut not the full usb elect?ical cha?acte?istics which will expe?ience deg?adation in the ?.? v to 3.0 v voltage ?ange. 3. r l is the inte?nal ?esiste? load connected to the usb d?ive? usbdp. t ? t f 90% 90% 10% 10% fall time rise time v crs figure 16. usb signal rise time and fall time and cross-point voltage (v crs ) defnition table 28. usb ac electrical characteristics symbol parameter conditions min. typ. max. unit t ? rise ti?e c l = 50 pf 4 ?0 ns t f fall ti?e c l = 50 pf 4 ?0 ns t ?/f rise ti?e / fall ti?e ?atching t ?/f = t ? / t f 90 110 % rev. 1.00 51 of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 electrical characteristics package information 6 package information note that the package information provided here is for consultation purposes only. as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package/carton information . additional supplementary information with regard to packaging is listed below. click on the relevant section to be transferred to the relevant website page. package information (include outline dimensions, product tape and reel specifcations) the operation instruction of packing materials carton information rev. 1.00 5? of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 package information saw type 46-pin (6.5mm4.5mm) qfn outline dimensions symbol dimensions in inch min. nom. max. a 0.031 0.033 0.035 a1 0.000 0.001 0.00? a3 0.008 bsc ? 0.006 0.008 0.010 d 0.?54 0.?56 0.?58 e 0.1?5 0.1?? 0.1?9 e 0.016 bsc d? 0.19? 0.?01 0.?05 e? 0.118 0.1?? 0.1?6 l 0.01? 0.016 0.0?0 symbol dimensions in mm min. nom. max. a 0.80 0.85 0.90 a1 0.00 0.0? 0.04 a3 0.?0 bsc ? 0.15 0.?0 0.?5 d 6.45 6.50 6.55 e 4.45 4.50 4.55 e 0.40 bsc d? 5.00 5.10 5.?0 e? 3.00 3.10 3.?0 l 0.30 0.40 0.50 rev. 1.00 53 of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 package information package information 48-pin lqfp (7mm7mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.354 bsc b 0.??6 bsc c 0.354 bsc d 0.??6 bsc e 0.0?0 bsc f 0.00? 0.009 0.011 g 0.053 0.055 0.05? h 0.063 i 0.00? 0.006 j 0.018 0.0?4 0.030 k 0.004 0.008 0 D ? symbol dimensions in mm min. nom. max. a 9.0 bsc b ?.0 bsc c 9.0 bsc d ?.0 bsc e 0.5 bsc f 0.1? 0.?? 0.?? g 1.35 1.4 1.45 h 1.60 i 0.05 0.15 j 0.45 0.60 0.?5 k 0.09 0.?0 0 D ? rev. 1.00 54 of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 package information 64-pin lqfp (7mm7mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.354 bsc b 0.??6 bsc c 0.354 bsc d 0.??6 bsc e 0.016 bsc f 0.005 0.00? 0.009 g 0.053 0.055 0.05? h 0.063 i 0.00? 0.006 j 0.018 0.0?4 0.030 k 0.004 0.008 0 D ? symbol dimensions in mm min. nom. max. a 9.00 bsc b ?.00 bsc c 9.00 bsc d ?.00 bsc e 0.40 bsc f 0.13 0.18 0.?3 g 1.35 1.40 1.45 h 1.60 i 0.05 0.15 j 0.45 0.60 0.?5 k 0.09 0.?0 0 D ? rev. 1.00 55 of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 package information package information 100-pin lqfp (14mm14mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.630 bsc b 0.551 bsc c 0.630 bsc d 0.551 bsc e 0.0?0 bsc f 0.00? 0.009 0.011 g 0.053 0.055 0.05? h 0.063 i 0.00? 0.006 j 0.018 0.0?4 0.030 k 0.004 0.008 0 D ? symbol dimensions in mm min. nom. max. a 16.00 bsc b 14.00 bsc c 16.00 bsc d 14.00 bsc e 0.50 bsc f 0.1? 0.?? 0.?? g 1.35 1.40 1.45 h 1.60 i 0.05 0.15 j 0.45 0.60 0.?5 k 0.09 0.?0 0 D ? rev. 1.00 56 of 56 ?ove??e? 0?? ?01? 3?-bit a?? ? co?tex ? -m3 mcu ht3?f1?365/ht3?f1?366/ht3?f??366 package information copy?ight ? ?01? ? y holtek semico? ductor i?c. the info ?? ation appea? ing in this data sheet is ? elieved to ?e accu? ate at the ti? e of pu?lication. howeve ?? holtek assu?es no ?esponsi?ility a?ising f?o? the use of the specifications desc?i? ed. the applications ?entioned he?ein a?e used solely fo? the pu ? pose of illust? ation and holtek ? akes no wa?? anty o? ?ep? esentation that such applications will ?e suita?le without fu?the? ?odification? no? ?eco?? ends the use of its p ? oducts fo? application that ?ay p? esent a ? isk to hu? an life due to ? alfunction o? othe?wise. holtek's p?oducts a?e not autho?ized fo? use as c?itical co? ponents in life suppo? t devices o? syste? s. holtek ?ese? ves the ? ight to alte? its p? oducts without p?io? notifcation. for the most up-to-date information, please visit our web site at http://www. holtek.co?/en/. |
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